1. Field of the Invention
The present invention relates to a memory cell and a fabricating method thereof. More particularly, the present invention relates to a non-volatile memory and a fabricating method thereof.
2. Description of Related Art
Recently, demands on electrical consumers are increasing. Most of the electrical consumers including digital cameras, MP3 players, laptop computers and personal digital assistants (PDAs) require read-only memories (ROMs) for storing a great deal of data. Since information or the data stored in the ROM are not volatiled even though the power is off, the ROM is also called a non-volatile memory. The most common ROM goes to an electrically erasable programmable ROM (EEPROM) which is not only capable of reading and writing but also allows multiple programming and erasing operations.
The typical EEPROM adopts doped polysilicon as a control gate and a floating gate. During a programming operation performed on the EEPROM, electrons injected into the floating gate may be distributed over the whole doped polysilicon floating gate layer in a uniform manner. However, when there are defects in a tunneling oxide layer under the doped polysilicon floating gate layer, current leakage of the device may occur, and the reliability of the device is adversely affected.
Currently, the issue of current leakage occurring in the EEPROM may be resolved with use of a certain device. This device employs a charge trapping layer as a replacement for the doped polysilicon floating gate layer. Since the charge trapping layer is made of a material characterized by capturing the electrons, the electrons injected into the charge trapping layer are not uniformly distributed over the charge trapping layer. Instead, the electrons with a Gaussian distribution property are collected in partial areas of the charge trapping layer. Since the electrons injected into the charge trapping layer are merely concentrated in the partial areas, said charge trapping layer has little sensitivity to the defects of the tunneling oxide layer, thus lessening the current leakage of the device. Typically, the material of the charge trapping layer is silicon nitride. The charge trapping layer made of silicon nitride is normally sandwiched between a top silicon oxide layer and a bottom silicon oxide layer to form a stacked gate structure including a silicon oxide/silicon nitride/silicon oxide (ONO) composite dielectric layer. The EEPROM having said stacked gate structure is frequently referred to as a silicon nitride ROM. However, the number of the charges captured by the charge trapping layer made of silicon nitride and the capturing speed of the charge trapping layer are not quite impressive.